Open Access Conference Proceedings

The rapid evolution of nanoelectronics underscores the need for innovative field-effect transistor (FET) architectures that deliver enhanced performance and enable further miniaturization. This study investigates the design and fabrication potential of a multilayer nanosheet metal-dielectric-semiconductor (MDS) transistor, utilizing semiconducting graphene layers deposited on a silicon substrate and incorporating gold source and drain regions. The graphene layers form contacts with both the upper and lower surfaces of the gold electrodes, resulting in a multilayered gate and channel structure. This configuration allows the gate to fully enclose the channel, thereby improving electrostatic control and optimizing transistor performance parameters. A comprehensive technological modeling process was conducted to define the fabrication sequence, yielding a structure composed of vertically stacked graphene channels encapsulated by silicon dioxide and polycrystalline silicon. Additionally, the study explores a cost-effective and scalable method for depositing graphene layers. This approach involves exfoliating graphite into particles containing varying numbers of graphene layers, which are then dispersed in a liquid medium. Using sharp-edged, blade-shaped probes, these particles are selectively transferred onto the substrate surface, enabling the formation of grapheme layers with controlled thickness and dimensions. The findings demonstrate that the proposed structure and fabrication method can facilitate the development of compact, high-speed MDS transistors, significantly broadening the practical applications of graphene in nano-electronic devices.

Keywords: Graphene, nanoelectronics, field-effect transistor, metal–dielectric–semiconductor, nanosheet structure

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